Semiconductor memory devices typically include one or more memory arrays, each of which includes large number of memory cells arranged in rows and columns. The memory cells are accessed by the application of an address, which results in the selection of a row and a column (or a group of columns). Commonly, memory cells within the same row are coupled to a word line, while memory cells within the same column are coupled to a bit line (or bit line pair). In response to a row address, a given word line will be activated, coupling a row of memory cells to their respective bit line. In response to a column address, selected bit lines are coupled to an input/output (I/O) bus, allowing data to be read from, or written to, the selected memory cells.
While semiconductor device manufacturing processes continue to improve, manufacturing induced defects can still occur. Such defects can arise from uncontrollable process variations or particulate contamination. For the most part, these defects are not catastrophic, and only give rise to a limited number of nonfunctional memory cells within an array. To prevent such relatively small defects from destroying a memory device, it is common practice to employ "redundant" memory cells.
Redundant memory cells are extra memory cells that can be used to replace defective memory cells. In this manner, a device can essentially repair itself by accessing the redundant memory cells instead of the defective memory cells. A redundancy scheme can include row-wise redundancy and/or column-wise redundancy. In the case of row-wise redundancy, one or more extra rows of memory cells are created within the array. In the event an applied memory address corresponds to a row having a defective memory cell, one of the extra rows of memory cells is accessed in place of the row containing the defective memory cell. In the case of column-wise redundancy, the extra columns of memory cells are created within the array. In a memory access operation, the bit line associated with the extra column is coupled to an I/O bus, in place of the bit line of a column having defective memory cells.
To access selected bit lines within a memory cell array, a semiconductor memory device usually includes a column decoding circuit. The column decoding circuit receives the column address, and activates a particular column select signal according to the values of the column address. For example, in the event the column address includes 8-bits, the column decoder would activate one out of 2.sup.8 column select signals. The speed at which the column decoder can select a given column address (i.e., decode the address) can play an important role in the overall speed of the device.
When column redundancy schemes are employed, the semiconductor memory device must incorporate column redundancy circuits into the column decoding scheme. A common circuit item for such redundancy schemes is a redundancy decoder circuit for comparing the incoming column address with a known bad address (address of a column having a defective cell or cells). If a match occurs, the semiconductor memory device accesses a redundant column instead of the known bad column. The location of a defective column address is determined by testing the device after it has been manufactured, and then programming defective address location(s), often by way of fusible links or like, into the decoder circuit.
Referring now to FIG. 1, a prior art redundancy scheme is set forth in schematic block diagram. The block diagram is designated by the general reference character 100 and is shown to include a pre-decoder circuit 102 that receives a column address. The pre-decoder circuit 102 provides an initial level of decoding to generate "column factors." Such pre-decoding typically consists of an initial set of logic gates to combine groups of address bits with one another. The output of the pre-decoder circuit 102 is shown in FIG. 1 as "PRED COLADD." It is noted that the number of PRED COLADD values is greater than the number of COLADD values.
The PRED COLADD signals are applied to a standard column decoder 104 and a compare/decoder circuit 106. In addition to the PRED COLADD signals, the compare/decoder circuit 106 also receives a pre-decoded defective column address RED COLADD. The RED COLADD address is provided by a fuse circuit 108. The fuse circuit 108 includes a fusible link corresponding to each RED COLADD signal. In order to generate the RED COLADD signal, selected of the fusible links within the fuse circuit 110 are either opened, or kept intact, to establish the logic of the RED COLADD signals.
When the RED COLADD signals do not match the PRED COLADD signals, a "no match" signal is activated which enables the standard column decoder 104. The standard column decoder 104 will then activate a standard column select signal (COL0-COLz) corresponding to the PRED COLADD signal. In contrast, when the RED COLADD signals match the PRED COLADD signals, a "match" signal is activated. The match signal serves as a redundant column enable signal RED COL.
A drawback to the prior art redundancy scheme of FIG. 1 is the large number of fuses required to generate the pre-decoded defective column address RED COLADD. As noted above, the number of signals required to generate a pre-decoded address is greater than the number of address signals. Further, each fuse can consume significant space on the memory device. For example, a laser fusible link may require a minimum spacing from other device structures due to the spot size of the laser, and/or require a relatively large area oxide window over the fusible link. Such requirements add to the size of the semiconductor memory device.
In addition, the current fusible links and/or "anti-fuse" structures may require additional circuits to ensure that appropriate current and/or voltage signals are applied to the fusible link. Such additional circuits also add to the size of the semiconductor device. Further, anti-fuse structures can require specialized processing steps. Therefore, the implementation of FIG. 1 can require considerable area or additional process steps to implement.
A further drawback to the redundancy arrangement of FIG. 1 is the timing requirements necessary to ensure proper operation. In the event the "no match" and "match" signals are activated close together in time, the simultaneous activation of a standard column select signal (COL0-COLz) can occur, resulting in an erroneous operation (glitch).
One way to reduce the number of fuses required to implement a redundancy scheme is to compare/decode the applied undecoded address. An example of a NOR-type decoding arrangement is set forth in FIG. 2 in a detailed schematic diagram. The NOR-type decoder 200 receives the results of a bit-by-bit comparison between the defective column address (RED COLADD0-RED COLADDn) and the applied column address (COLADD0-COLADDn). In the particular example of FIG. 2 the comparison is equivalent to a XOR function. Each bit-by-bit comparison is applied to the gate of a pull-down transistor (N200-N20n) having a source-drain path coupled between the low power supply voltage VSS, and a pre-charge node 202. The pre-charge node 202 is precharged to the high power supply voltage VCC by a pre-charge signal PRECH.sub.--. The pre-charge operation is accomplished by a pre-charge transistor P200 having a gate which receives the PRECH.sub.-- signal and a source-drain path coupled between the pre-charge node 202 and the high power supply voltage.
In operation, the PRECH.sub.-- signal is initially low, pulling the pre-charge node 202 high. Subsequently, a column address (COLADD0-COLADDn) is applied and compared on a bit-by-bit basis with the fuse programmed defective address (RED COLADD0-RED COLADDn). The resulting bit comparisons are applied to the gates of transistors N200-N20n. In the event the applied address is different from the defective address, at least one of the bit-by-bit comparisons will be high, and activate its associated pull-down transistor. The pre-charge node 202 will be pulled low, and inverter 1200 will generate a high standard access signal STD. The high STD signal enables the standard (i.e., non-redundant) column select devices within the memory device. In the event the applied address is the same as the defective address, all of the bit-by-bit comparisons will be low, and none of the pull-down transistors (N200-N20n) will be turned on. The pre-charge node 202 will remain high and produce a high redundant enable signal RED. The RED signal, in combination with other timing signals, will activate a redundant column.
While the redundancy arrangement illustrated in FIG. 2 requires fewer fuses to implement, the NOR-type decoder can produce disparities in timing according to the values of the bit comparisons. There may also be differences in timing between the standard accesses and redundant accesses. For example, there may be a particularly "fast" standard access in which nearly all of the bit-by-bit comparisons are high. As a result nearly all of the pull-down transistors (N200-N20n) are on, providing for rapid discharge of the pre-charge node 202. Conversely, a standard case may result in a relatively "slow" timing, when all but one of the bit-by-bit comparison signals are low. In such a case, only one of the pull-down transistors (N200-N20n) will be turned on, requiring more time to discharge the pre-charge node 202. Finally, because no discharge operation is required, the RED signal is already high, and the redundant access may be accomplished faster than any of the standard accesses.
It would be desirable to provide a redundant column decoder that does not require considerable area for fusible link structures. Further, it would also be desirable to provide a redundant column decoder that does not suffer from timing disparities between standard column accesses and redundant column accesses.